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An all-digital PLL using frequency multiplying/dividing number with decimals in 0.18-μm digital CMOS

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3 Author(s)
Watanabe, T. ; Corp. R&D Dept. 2, DENSO Corp., Kariya ; Yamauchi, S. ; Terasawa, T.

An all-digital PLL that generates arbitrary output clock frequencies with only one reference clock frequency is presented. The method adopted in this study uses multiplying/dividing numbers with decimals. A ring-delay-line (RDL) consisting of 32 stages makes it possible for both the frequency detector and digitally-controlled oscillator to have a common time base, resulting in this unique clock generator. Evaluation experiments were conducted using a 0.18-mum CMOS test chip of 0.096 mm2. In the case of a reference clock frequency of 60 kHz and multiplying number of 16.666, we confirmed a 999.96 kHz output clock with 11.6 ppm frequency error and 540 ps jitter standard deviation.

Published in:

Frequency Control Symposium, 2008 IEEE International

Date of Conference:

19-21 May 2008