Cart (Loading....) | Create Account
Close category search window

Low-Power AES Design Using Parallel Architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Hyun Suk Choi ; Sch. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon ; Joong Hyun Choi ; Jong Tae Kim

This paper presents a design of AES (advanced encryption standard) with parallel architecture. The proposed architecture maintains throughput as it is but consumes lower power than the original architecture by using 1/2 clock-rate and reducing supply voltage. Models were designed using VHDL and verified by both functional and gate-level simulation. They were logically synthesized using 0.25 um, 90 nm cell library by Synopsys Design compiler. Power consumption was computed by Synopsys PrimePower.

Published in:

Convergence and Hybrid Information Technology, 2008. ICHIT '08. International Conference on

Date of Conference:

28-30 Aug. 2008

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.