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Low-Power AES Design Using Parallel Architecture

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3 Author(s)
Hyun Suk Choi ; Sch. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon ; Joong Hyun Choi ; Jong Tae Kim

This paper presents a design of AES (advanced encryption standard) with parallel architecture. The proposed architecture maintains throughput as it is but consumes lower power than the original architecture by using 1/2 clock-rate and reducing supply voltage. Models were designed using VHDL and verified by both functional and gate-level simulation. They were logically synthesized using 0.25 um, 90 nm cell library by Synopsys Design compiler. Power consumption was computed by Synopsys PrimePower.

Published in:

Convergence and Hybrid Information Technology, 2008. ICHIT '08. International Conference on

Date of Conference:

28-30 Aug. 2008

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