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This paper presents a design of AES (advanced encryption standard) with parallel architecture. The proposed architecture maintains throughput as it is but consumes lower power than the original architecture by using 1/2 clock-rate and reducing supply voltage. Models were designed using VHDL and verified by both functional and gate-level simulation. They were logically synthesized using 0.25 um, 90 nm cell library by Synopsys Design compiler. Power consumption was computed by Synopsys PrimePower.