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Top Level SOC Interconnectivity Verification Using Formal Techniques

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1 Author(s)
Roy, S.K. ; Texas Instrum. India, Bangalore

SOCs are designed by integrating existing in house cores/intellectual properties (IPs), or third party core/IPs provided by external vendors to reduce design turn-around time and cost. The integration process in realizing an SOC implementation consists of several different kinds of integration which can be classified as (1) static or non-functional integration, consisting of simple electrical connections (or hookup) of the inputs and outputs of different IPs, and (2) dynamic, or functional integration, where, besides the pure electrical connectivity, a temporal and a functional dimension needs to be taken into account. Given the size of present generation SOCs there is ample scope of inadvertent design errors being introduced during the integration process. It has been observed in many in-house SOC designs that a large percentage of these errors (80%) are contributed by pure connectivity errors. Severity of implications of some of these errors, are dependent on when they are detected in the design verification cycle, and on how easy it is to correct them in the implementation. In this paper, we present the challenges involved in detecting such integration errors in complex SOCs through the use of formal verification techniques. The main contributions of this work are (1) effective use of formal techniques based on symbolic model checking in the top level verification of SOC integration, (2) effective use of abstraction and modeling of SOC sub-systems in enabling assertion based formal verification, (3) automated generation of assertions and constraints to detect integration errors, (4) automated generation of scripts to capture the SOC design information and invoke a formal verification tool on which to prove the validity or correctness of these assertions, and (5) case studies from different categories of SOC integration to highlight the benefits of the proposed approach. These techniques have been applied to verify different kinds of integration described above in- - several SOCs designed in Texas Instruments, with promising results.

Published in:

Microprocessor Test and Verification, 2007. MTV '07. Eighth International Workshop on

Date of Conference:

5-6 Dec. 2007