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High level testability analysis using VHDL Automatic Test Pattern Generation

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4 Author(s)
Giamarchi, F. ; SPE UMR CNRS 6134 Lab., Univ. of Corsica, Corte ; Capocchi, L. ; Federici, D. ; Bisgambiglia, P.A.

This paper is about problems of testability of circuits. In account of the progress achieved in the field of integration, we are in presence of increasingly complex circuits. So to pose the problem of testability and maintenance, from the phase of the circuit design is the means more adapted in order to improve them and make it possible to carry out the test at a reasonable cost. In this article we present an automatic test pattern generator using discrete event modeling methodology for the simulation of behavioral faults of VHDL, called ATPG-DEVS.

Published in:

Electrotechnical Conference, 2008. MELECON 2008. The 14th IEEE Mediterranean

Date of Conference:

5-7 May 2008