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In this paper, we investigate the performance of on-chip interconnect constructed using hybrid systems containing both single-walled carbon nanotube (SWCNT) based driver transistors and SWCNT bundle-based wires. Leveraging an equivalent circuit model for SWCNT bundle-based interconnect and a semi-empirical model for both N-type and P-type carbon nanotube field effect transistors (CNTFET), we predict the performance of hybrid systems of nanotube-based devices and interconnect using circuit-level simulation. The results indicate that hybrid nanotube-based driver/interconnect systems can potentially provide a substantial delay reduction over standard CMOS buffers and copper interconnect implemented in 22 nm process technology. Finally, we examine the reliability implications of parasitic metallic nanotubes in CNTFET-based driver circuits and find that even a small number of parasitic metallic nanotubes can lead to logic failures, which underscores the need for tight process control when manufacturing CNTFETs.