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This paper presents a novel asynchronous architecture of field-programmable gate arrays (FPGAs) to reduce the power consumption. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To reduce the static power due to leakage current that is now comparable to the dynamic one, we propose a fine-grained power-gating scheme at each Look-up table (LUT). The proposed field-programmable VLSI is fabricated in a 90 nm CMOS technology. Its power consumption is reduced to 42% compared to synchronous architecture.