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This paper reports the transistor-level design of a continuous-time 2-1 MASH sigma delta modulator with digital adaptive tuning of the cancellation logic. The modulator is designed for broadband wireless applications and provides 12 bits of resolution for a 10 MHz signal bandwidth. A direct approach to design the CT MASH modulator is used which reduces the coupling between the MASH stages. The problems of excess loop delay and clock jitter are addressed. Excess delay compensation loops are used to overcome the problem of excess loop delay. Multi-bit quantizers with NRZ DACs are used to reduce the effect of clock jitter. It is shown that without calibration, the performance of a CT MASH modulator would be severely degraded due to different analog imperfections such as finite gain and bandwidth of the Opamp, clock jitter and even addition of the excess delay compensation loops. The catastrophic degradation is due to the leakage of lower order noise to the output of the modulator. An adaptive digital tuning of the digital filters is used in this design to regain the performance of the modulator in presence of the above errors. Simulation results show that the modulator provides the required resolution while consuming 20 mW of power from 1.8 V supply voltage.