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Static random access memory (SRAM) circuits optimized for minimum energy consumption typically operate in the subthreshold regime with ultra-low power-supply-voltages. Both the read and the write propagation delays of a subthreshold memory circuit are significantly reduced with an increase in the die temperature. The excessive timing slack observed in the clock period of constant-frequency subthreshold memory circuits at elevated temperatures provides new opportunities to lower the active mode energy consumption. Temperature-adaptive dynamic supply voltage tuning technique is proposed in this paper to reduce the high temperature energy consumption of ultra-low-voltage subthreshold SRAM arrays. Results with a 64-bit times 64-bit memory array in the TSMC 180 nm CMOS technology indicate that the energy consumption can be lowered by up to 32.8% by dynamically scaling the supply voltage at elevated temperatures.
Date of Conference: 10-13 Aug. 2008