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Area and power optimization of a first-order delta-sigma analog-to-digital converter (ADC) for pixel-level data conversion is presented. The ADC is designed for use in a vertically-integrated logarithmic CMOS image sensor. A switched-capacitor modulator with minimum area has been employed. Unlike other similar structures, the decimation is performed inside the pixel to decrease its output bit rate. The proposed ADC has an area of 32 times 31 mum2 and consumes 680 nW of power to achieve 80 dB of signal-to-noise ratio with a frame rate of 50 Hz. The circuit was implemented in 0.18 mum CMOS technology with a die area of 2 mm2 and has been sent for fabrication.