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A fault-tolerant FFT processor

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2 Author(s)
Choi, Y.-H. ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA ; Malek, M.

A method is proposed for achieving fault tolerance by introducing a redundant stage for a special-purpose fast Fourier transform (FFT) processor. A concurrent error-detection technique, called recomputing by alternate path, is used to detect errors during normal operation. Once an error is detected, a faulty butterfly can be located with log (N +5) additional cycles. The method has 100% detection and location capability, regardless of the magnitude of the roundoff errors. A gracefully degraded reconfiguration using a redundant stage is introduced. This technique ensures a high improvement in reliability and availability. Hardware overhead is O(1/log N) with some additional comparators and switches. The method can be applied to other algorithms implementable on the butterfly structure

Published in:

Computers, IEEE Transactions on  (Volume:37 ,  Issue: 5 )

Date of Publication:

May 1988

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