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Modulo 3 residue checker: new results on performance and cost

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2 Author(s)
Watterson, J.W. ; Center for Digital Syst. Res., Res. Triangle Inst., Research Triangle Park, NC, USA ; Hallenbeck, J.J.

The performance and cost of a modulo-3 residue code checker that has been attached to a pipelined serial multiplier to provide a concurrent self-test capability are considered. Analytical results are derived for error detection coverage and minimum error latency; these quantities are observed to be in agreement with simulation results obtained by using ISPS, a register-transfer language. The residue checker error detection coverage and minimum error latency are observed to be dependent on the statistical properties of the multiplier input operands. The checker and serial multiplier were implemented in 4-μm NMOS, using a standard cell design. The residue code checker required approximately half of the total silicon area

Published in:

Computers, IEEE Transactions on  (Volume:37 ,  Issue: 5 )

Date of Publication:

May 1988

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