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Calibration of sampling clock skew in SHA-less pipeline ADCs

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2 Author(s)
Huang, P. ; Dept. of Electr. & Comput. Eng., UIUC, Urbana, IL ; Chiu, Y.

A gradient-based algorithm to adaptively calibrate sampling clock skew in sample-and-hold amplifier (SHA)-less pipeline analogue-to-digital converters (ADCs) is presented. It follows that the power consumption of pipeline ADCs can be substantially reduced at the architecture level by employing the SHA-less multi-bit-per-stage architecture and remedying the resulting sampling clock skew problem with calibration.

Published in:

Electronics Letters  (Volume:44 ,  Issue: 18 )