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Flying-adder frequency synthesis architecture is a novel technique of generating frequency on chip. Since its invention, it has been utilized in many commercial products to cope with various difficult challenges. During the evolution of this architecture, the issues related to circuit- and system-level implementation have been studied in prior publications. However, rigorous mathematical treatment on this architecture has not been established. In this paper, we attempt to explore and understand the signal characteristics and frequency domain behavior of this architecture through mathematical analysis. In the meantime, the underlying concept associated with this architecture, time-average-frequency, is formally introduced.