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Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware

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3 Author(s)
J. Wang ; Department of Information and Communication Engineering, Inha University, Incheon, Republic of Korea ; Q. S. Chen ; C. H. Lee

The authors present a novel virtual reconfigurable architecture (VRA) for realising real-world applications of intrinsic evolvable hardware (EHW) on field programmable gate arrays (FPGAs). The phenotype representation of the proposed evolvable system is based on a two-dimensional function element (FE) network. Compared with the traditional Cartesian genetic programming, the proposed approach includes more connection restrictions in the FE network to reduce genotype length. Another innovative feature of the VRA is that the whole evolvable system, which consists of an evolutionary algorithm unit, a fitness value calculation unit and an FE array unit, can be realised on a single FPGA. On this work, a custom Xilinx Virtex xcv2000E FPGA, which is fitted in the Celoxica RC1000 peripheral component interconnect (PCI) board is utilised as the hardware platform. The main motive of the research is to design a general, flexible evolvable system with powerful computation ability to achieve intrinsic evolution. As examples, the proposed evolvable system is devoted to evolve two real-world applications: a character recogniser and an image operator by using gate level evolution and function level evolution, respectively. The experimental results show that the VRA can bring higher computational ability and more flexibility than traditional approach to intrinsic EHW.

Published in:

IET Computers & Digital Techniques  (Volume:2 ,  Issue: 5 )