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Exploring architectural solutions for energy optimisations in bus-based system-on-chip

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6 Author(s)
Srinivasan, S. ; Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA ; Li, L. ; Ruggiero, M. ; Angiolini, F.
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System-on-chip (SoC) architectures have emerged as ubiquitous option for computation-intensive applications because of the tremendous flexibility provided by them with respect to design reuse and extendibility. Single shared bus architectures have been popularly used as communication channel in such on-chip architectures, by connecting various modules in such systems. However, increasing levels of integration and the number of components connected to the bus render such architectures infeasible. Consequently, such single shared bus architectures fail to scale well with both performance and power aspects. The authors demonstrate here a way to perform memory and bus partitioning and allocate variable frequencies to different bus segments to reduce the power consumption of the system without affecting the performance. The authors use an evolutionary algorithm followed by an iterative search-based frequency allocation algorithm to solve the problem. The effectiveness of the proposed results is validated on a SystemC-based cycle-accurate bus-based SoC simulator.

Published in:

Computers & Digital Techniques, IET  (Volume:2 ,  Issue: 5 )