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Hardware implementation of a stereo co-processor in a medium-scale field programmable gate array

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2 Author(s)
J. A. Kalomiros ; Department of Informatics and Communications, School of Technological Applications, Serres Institute of Education ; J. Lygouras

The design of a hardware co-processor for stereo depth detection, based on a parallel implementation of the sum of absolute differences algorithm, is presented. Model-based designs are followed, and a parameterisable open source VHDL library component appropriate for integration within a system-on-a- programmable chip is created. We target a field programmable gate array board featuring external memory and other peripheral components and implement the control path with a Nios II embedded processor clocked at 100 MHz. The hardware co-processor produces dense 8-bit disparity maps of 320times240 pixels at a rate of 25 Mpixels/s and can expand the disparity range from 32 to 64 pixels with appropriate memory techniques. Essential resources can be as low as 16 000 logic elements, whereas by migrating to more complex devices the design can easily grow to support better results.

Published in:

IET Computers & Digital Techniques  (Volume:2 ,  Issue: 5 )