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Parallelization of H.264 video decoder for embedded multicore processor

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3 Author(s)
Kosuke Nishihara ; System IP Core Research Laboratories, NEC Corporation, Japan ; Atsushi Hatabu ; Tatsuji Moriyoshi

This paper presents two parallelization methods for H.264 video decoder software on an embedded multicore processor. In parallelizing the H.264 video decoder software on a typical embedded multicore processor with shared memory, there are two problems. One problem is the computational load imbalance among cores. The other problem is memory access contention. The first method is coarse, flexible partitioning adapted for the H.264 decoding functions, which can balance the load with only a small number of synchronizations. The second method is preloading based on predicting the execution time, which can reduce memory access contention and the redundant waiting time for other cores. Experimental results demonstrate that our proposed two methods can achieve significant improvement of the consumed cycles for decoding H.264 bitstreams of QVGA size from 217 to 96 Mcps (2.3 times speedup) as compared to a non-parallel decoder.

Published in:

2008 IEEE International Conference on Multimedia and Expo

Date of Conference:

June 23 2008-April 26 2008