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The optimization of hierarchical SOC test architecture to reduce test time

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2 Author(s)
Xu Chuan-pei ; Sch. of Electron. Eng., Guilin Univ. of Electron. Technol., Guilin ; Dai Kui

Modular testing of SOCs mainly concentrates in the SOC test architecture and test structure optimization. At present, most of the studies are based on the assumed flattened SOC. This does not meet the needs of practice SOC, because most actual SOCs are of the structure of layers due to the universal use of the reuse technique. On the basis of IEEE P1500 ring based TAM and test bus based CTW this paper researches on multilevel TAM structures of hierarchical SOC. That two obedience certification of IEEE P1500 and two design processes of hierarchical SOC makes that IP core form providers can be provided in different ways to the SOC integrators. On the basis of the four layer model of SOC test architecture optimization, hierarchical SOC test architecture optimization model is presented according to classifications. This paper adopts black box idea to fuzzy hierarchical sub-core and single-core PW problems, and puts the flattened SOC test architecture optimization and hierarchical SOC test architecture optimization together in a same test framework. From a macroscopical view, this test framework ignores the structure changing inside of the black box, simplifies the multilevel TAM optimization and has a good scalability to various IP core; from a microscopical view, finely deals with the different IP sub-core in the black box, and extends downwards by levels, so that achieves the goal of multilevel TAM optimization finally. Based on the test architecture research of hierarchical SOC, the paper applies quantum-inspired evolutionary algorithm to SOC test architecture optimization, and establishes a heuristic process based on a property assumption of searching arithmetic to solve the PPAW . Through the observation of group, QEA can decide the allocation of IP core on TAM and the best individual of the current group, and gradually find the overall best individual by using the updated operation. The heuristic process significantly saves the time of CPU co- - mputing. The paper has partial hierarchical SOC in ITCpsila02 Test Benchmark as experimentation objects to make the simulation experiments. Experimental results and the results of other algorithms are compared, and the algorithm gets a comparatively short testing time.

Published in:

Electronic Packaging Technology & High Density Packaging, 2008. ICEPT-HDP 2008. International Conference on

Date of Conference:

28-31 July 2008

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