By Topic

Combinational test generation for transition faults in acyclic sequential circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Shi Hui ; Key Lab. of Adv. Displays & Syst. Applic., Shanghai Univ., Shanghai ; Ran Feng ; Zhang Jinyi

This paper presents a combinational test generation method for transition faults in acyclic sequential circuits. In this method, to generate test sequences for transition faults in a given acyclic sequential circuit is performed on its extend time-expansion model. The model is composed of two copies of time-expansion model of the given circuit and extends in the close two sequences to generate 2 vectors for the transition faults with some restrictions. Experimental results show the method can achieve the higher fault efficiency with the lower test generation times than conventional method.

Published in:

Electronic Packaging Technology & High Density Packaging, 2008. ICEPT-HDP 2008. International Conference on

Date of Conference:

28-31 July 2008