By Topic

A verification method based on a mixed-signal system for MV06

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Hu Yue-li ; Sch. of Mechatron. & Autom., Shanghai Univ., Shanghai ; Zhang Yi-chi ; Xuan Xiang-guang

With the rapid development of mixed-signal system-on-chip (SOC), the verification before tape-out is a critical phase during the design flow in order to guarantee the products yield. A design flow based on mixed-signal verification is proposed. Exemplified with the design of a mixed MCU (MV06), this paper proposes the verification precept and introduces the simulation principle and method of mixed signals in the synopsys simulation environment, and then describes the simulation process with the discovery AMS and presents the verification result. This methodology is implemented in our tape-out, the feasibility and efficiency of the method has been verified.

Published in:

Electronic Packaging Technology & High Density Packaging, 2008. ICEPT-HDP 2008. International Conference on

Date of Conference:

28-31 July 2008