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Multi-core processor is becoming popular today. As the number of the core increase, the communications among cores also become complex and difficult. Caches are used in multi-core processors for sharing data and increasing performance. It becomes a channel for cores to communicate with each other. Intelpsilas next generation multi-core processor Nehalem which using an inclusive L3 cache to enhances the performances. This paper describes the function of the inclusive cache in the Nehalem and analyzes advantage of the MESIF cache coherence protocol by comparing with the standard MESI protocol. This paper also gives a structure of the cache that can be used to implement. The control flow is analyzed in order to ensure the operation of read/write cache will accord with the MESIF protocol.