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Advances in BGA packaging technologies have led to a dramatic increase in the performance of integrated circuits. Noise source such as supply bounce, signal coupling, and reflections results in reduced performance. The work presents techniques to model and improve performance the performance of BGA designs without moving toward advanced packaging. A single, unified mathematical framework is presented that predicts the performance of a given package depending on the package parasitics. Using 3-Bit Bus example about the package, a methodology is presented to analyse mutual inductive signal coupling and mutual capacitive signal coupling and return current. The performance model illustrate that the per-pin performance is significantly reduced, where the number of switching signals is increasing.