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A new panel base package (PBP) technology that was developed based on the concepts of the wafer level package (WLP) has been proposed in order to obtain the signal fan-out capability for the fine-pitched integrated circuit (IC). In the PBP, the chip is attached to a selected chip carrier, and the volume of IC devices is extended for the redistribution of the original die pads. In this study, the thermal performance of the PBP technology was investigated and discussed through three-dimensional finite element (FE) analysis. In order to compare the thermal performance between conventional WLP and the proposed PBP, the junction temperature of WLP was also recorded through the modified FE model. The results showed that due to the larger packaging size of the PBP structure, the added solder bumps can be used as thermal balls. Moreover, they can effectively reduce the packaging thermal resistance (from 55degC/W to 41degC/W). It is expected that thermal performance could be further improved by applying solder paste between the chip and chip carrier. The study likewise discussed the condition of forced convection and developed the PBP technology for high-density IC devices. In light of the results obtained from this study, we believe in our new PBB technologypsilas great potential for future applications.