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Using SOI double-gate MOSFET NDR structures to improve ultra-low power full adder performance

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4 Author(s)
Hassoune, I. ; Lyon Inst. of Nanotechnol., Lyon Univ., Ecully ; Yang, X. ; O'Connor, I. ; Navarro, D.

In this paper, we propose a new efficient design of a hybrid full adder cell combining two logic styles and a negative differential resistance (NDR) device realized in a fully depleted (FD) silicon on insulator (SOI) double-gate (DG) MOSFET technology. Simulation results show significant (65%) power savings for asymmetric gate workfunction and independent gate control full adders with respect to standard CMOS circuits, with lower device count and comparable delay figures.

Published in:

Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on

Date of Conference:

22-25 June 2008