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High-speed design of adaptive LDPC codes for wireless networks

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2 Author(s)
Zhiyong He ; Dept. of Electr. & Comput. Eng., Laval Univ., Quebec City, QC ; Roy, S.

In this paper, we propose a class of adaptive low-density parity-check (LDPC) codes for reliable data transmission in wireless networks, i.e. the code rate can be adapted according to channel conditions to maximize the total capacity. Constructed from shifted identity matrices, the first advantage of the proposed codes is that these codes are particularly well-suitable for the high-speed implementation of parallel encoders and parallel decoders. Since a unique mother parity check matrix is used to construct LDPC codes with several code rates, the second great advantage of the proposed codes is that a single universal encoder (decoder) is adequate to encode (decode) multi-rate codes, which makes it possible to efficiently implement multi-rate LDPC codes in a subscriber station. The implementation results into field programmable gate array (FPGA) devices indicate that a universal parallel encoder for LDPC codes with 9 code rates is capable of reaching a throughput above 3.6 Gigabit per second by using a clock frequency of 300 MHz and consuming only 1% of the total resources in a typical FPGA device.

Published in:

Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on

Date of Conference:

22-25 June 2008

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