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A 60GHz, 13 dBm fully integrated 65nm RF-CMOS power amplifier

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4 Author(s)
Sofiane Aloui ; IMS laboratory, UMR CNRS 5218, University of Bordeaux, 33405 Talence Cedex, France ; Eric Kerherve ; Didier Belot ; Robert Plana

A 65 nm CMOS, 60 GHz fully integrated power amplifier (PA) from STMicroelectronics has been designed for low cost Wireless Personal Area Network (WPAN). It has been optimized to deliver the maximum linear output power (OCP1) without using parallel amplification topology. The simulated OCP1 is equal to 8.9 dBm with a gain of 8 dB. To obtain good performances and consume an ultra compact area of silicon, the PA has been matched and optimized with a mixed technique, using lumped and distributed elements. The chip size is 0.48 mm*0.6 mm including pads.

Published in:

Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on

Date of Conference:

22-25 June 2008