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Iterative design method for video processors based on an architecture design language and its application to ELA deinterlacing

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3 Author(s)
Ngoyi, G.-A.B. ; Groupe de Rech. en Microelectron. et Microsyst., Ecole Polytech. de Montreal, Montreal, QC ; Langlois, J.M.P. ; Savaria, Y.

This paper presents a design methodology for dedicated real-time video processors. The methodology begins with a basic processor that is progressively morphed into a specialized processor through five systematic steps. It differs from standard methodologies for ASIP design which place exclusive emphasis on the extension of the instruction set. The proposed methodology takes a global look at various processor and system considerations. The last step consists of removing unnecessary functionality from the instruction set. The required flexibility is attained by the use of an architectural description language. We use a basic deinterlacing algorithm to demonstrate the effectiveness of the methodology and present details of the various phases of the design process. Using ELA deinterlacing as a benchmark, the final processor uses 20% fewer logic elements, achieves a global acceleration by a factor of 11, and an improvement in area-delay product of 14, with respect to the basic processor.

Published in:

Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on

Date of Conference:

22-25 June 2008