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Optimal parallel hardware architecture for discrete wavelet transform

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3 Author(s)
Liu Ying ; College of Automation, Harbin Engineering University, 150001, China ; Hao Yanling ; Wang Renlong

Optimal parallel hardware architecture for discrete wavelet transform is proposed in order to further decrease the hardware complexity of DWT. This architecture optimizes the parallel hardware architecture for discrete wavelet transform, introduces the method by prejudging the figure of the column and row in raw image instead of directly processing 2-D DWT on the row (column) wise, adopts 2times2 transposing link, and optimizes the scaling link by leading in 4 to 1 multiplexer. Experimental results show that the proposed architecture, under the tight critical path, can decrease the used resources of internal register and memory, at the same time save the arithmetic resources and hardware saving, and finally effectively lower the hardware complexity of the discrete wavelet transform.

Published in:

2008 27th Chinese Control Conference

Date of Conference:

16-18 July 2008