By Topic

Demonstration of L_{g} \sim \hbox {55} \hbox {nm} pMOSFETs With \hbox {Si/Si}_{0.25}\hbox {Ge}_{0.75}/\hbox {Si} Channels, High I_{\rm on}/I_{\rm \off} (\gg \hbox {5} \times \hbox {10}^{4}) , and Controlled Short Channel Effects (SCEs)

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

17 Author(s)
Se-Hoon Lee ; Univ. of Texas at Austin, Austin, TX ; Majhi, P. ; Jungwoo Oh ; Sassman, B.
more authors

High-performance sub-60 nm Si/SiGe (Ge:~75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high-kappa/metal gate stacks with ~1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length (L g) devices demonstrate not only controlled short channel effects, but also an excellent on-off current (I on/I off) ratio (~5times104 55-nm L g). The intrinsic gate delay of these heterostructures is ~3 ps at I on/I off~104. OFF-state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short L g devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.

Published in:

Electron Device Letters, IEEE  (Volume:29 ,  Issue: 9 )