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A Cost-Efficient Bit-Serial Architecture for Sub-pixel Motion Estimation of H.264/AVC

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3 Author(s)
Fatemi, M.R.H. ; Fac. of Comput. Sci. & Inf. Technol., Malaya Univ., Kuala Lumpur ; Ates, H.F. ; Salleh, R.

This paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation-free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter-pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 39%) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited.

Published in:

Intelligent Information Hiding and Multimedia Signal Processing, 2008. IIHMSP '08 International Conference on

Date of Conference:

15-17 Aug. 2008