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Memory built-in self test (MBIST) or as to it array built-in self test is an amazing piece of logic. Without any direct connection to the outside world, a very complex embedded memory can be tested efficiently, easily and less costly. Modeling and simulation of finite state machine (FSM) MBIST is presented in this paper. The design architecture is written in very high speed integrated circuit hardware description language (VHDL) code using Xilinx ISE tools. The architecture is modeled and synthesized using register transfer level (RTL) abstraction. Verification of this architecture is carried out by testing stuck at fault SRAM. A BIST algorithms is implemented i.e March C- to test the faulty SRAM.