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Code division multiple access (CDMA) is a rapidly expanding data transmission technique in the emerging universal mobile telecommunication system. Digital matched filter (DMF) in a CDMA system is used for correlating the received data with the transmitted data. The key issues in the design of a DMF are speed and power. This paper presents the design of a fine-grain pipelined DMF with clock gating with an objective to increase the speed and at the same time reduce the power consumption. The design has been verified through simulation and synthesis of the existing DMF and the proposed architectures. Verilog HDL coding of the design is done using Xilinx ISE design tool. Speed and estimated power consumption of the design are obtained using XST Synthesis and XPower tools of Xilinx respectively.