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Threshold-Voltage Reduction of FinFETs by Ta/Mo Interdiffusion Dual Metal-Gate Technology for Low-Operating-Power Application

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11 Author(s)
Matsukawa, T. ; Nanoelectron. Res. Inst., Tsukuba ; Endo, K. ; Yongxun Liu ; O'uchi, S.
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In this paper, Ta/Mo interdiffusion dual metal-gate technology, which has an advantage in realizing dual gate work functions without etching of metals from the gate dielectrics, has been introduced for a FinFET. Gate-first fabrication of the FinFET was successfully implemented by optimizing the deposition and patterning of the Mo and Ta/Mo metal gates on the ultra- thin fin channels. The Ta/Mo-gated n-MOS and Mo-gated p-MOS FinFET exhibit symmetrical values of Vth (0.31/-0.36 V), which are desirable for FinFET CMOS circuit operation with enhanced current drivability, because the threshold voltage (Vth) is reduced due to Ta diffusion in the Ta/Mo gate. It was experimentally found that the Ta/Mo interdiffusion process causes no degradation in integrity of the gate dielectric or the carrier mobility. It was also confirmed that the Ta/Mo interdiffusion process is appropriate for a scaled gate length down to 100 nm.

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Electron Devices, IEEE Transactions on  (Volume:55 ,  Issue: 9 )