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A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs

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2 Author(s)
Jyh-Chyurn Guo ; Inst. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu ; Yi Min Lin

A compact RF CMOS model incorporating an improved thermal noise model is developed. Short-channel effects (SCEs), substrate potential fluctuation effect, and parasitic-resistance-induced excess noises were implemented in analytical formulas to accurately simulate RF noises in sub-100-nm MOSFETs. The intrinsic noise extracted through a previously developed lossy substrate de-embedding method and calculated by the improved noise model can consistently predict gate length scaling effects. For 65- and 80-nm n-channel MOS with fT above 160 and 100 GHz, NFmin at 10 GHz can be suppressed to 0.5 and 0.7 dB, respectively. Drain current noise Sid reveals an apparently larger value for 65-nm devices than that for 80-nm devices due to SCE. On the other hand, the shorter channel helps reduce the gate current noise Sig attributed to smaller gate capacitances. Gate resistance Rg-induced excess noise dominates in Sig near one order higher than the intrinsic gate noise that is free from Rg for 65-nm devices. The compact RF CMOS modeling can facilitate high-frequency noise simulation accuracy in nanoscale RF CMOS circuits for low-noise design.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:27 ,  Issue: 9 )