By Topic

Diagnosis of Optical Lithography Faults With Product Test Sets

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Munkang Choi ; Synopsys, Inc., Mountain View, CA ; Linda Milor

Increasing within-die variation, combined with larger numbers of critical and near-critical paths and higher operating frequencies, has increased the sensitivity of chips to path delay faults. A component of within-die variation comes from optical lithography, including the optical proximity effect, lens aberrations, and flare. This paper presents a methodology to generate test sets to diagnose these sources of within-die variation. Specifically, a delay fault diagnosis algorithm is developed to link failing signatures to a set of physical mechanisms originating from lithography. The algorithm relies on layout-dependent timing analysis, path enumeration, test pattern generation, and correlation of pass/fail signatures to diagnose delay faults caused by lithography. The effectiveness of diagnosis is evaluated for ISCAS85 benchmark circuits.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:27 ,  Issue: 9 )