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Increasing within-die variation, combined with larger numbers of critical and near-critical paths and higher operating frequencies, has increased the sensitivity of chips to path delay faults. A component of within-die variation comes from optical lithography, including the optical proximity effect, lens aberrations, and flare. This paper presents a methodology to generate test sets to diagnose these sources of within-die variation. Specifically, a delay fault diagnosis algorithm is developed to link failing signatures to a set of physical mechanisms originating from lithography. The algorithm relies on layout-dependent timing analysis, path enumeration, test pattern generation, and correlation of pass/fail signatures to diagnose delay faults caused by lithography. The effectiveness of diagnosis is evaluated for ISCAS85 benchmark circuits.