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Whitespace redistribution for thermal via insertion in 3D stacked ICs

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2 Author(s)
Eric Wong ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA ; Sung Kyu Lim

One of the biggest challenges in 3D stacked IC design is heat dissipation. Incorporating thermal vias is a promising method for reducing the temperatures of 3D ICs. The bonding styles between device layers impose certain restrictions to where thermal vias may be inserted. This paper presents a whitespace redistribution algorithm that takes bonding style into consideration to improve thermal via placement, which in turn reduces temperature.

Published in:

Computer Design, 2007. ICCD 2007. 25th International Conference on

Date of Conference:

7-10 Oct. 2007

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