By Topic

A performance analysis for single-walled metallic Carbon Nanotubes as global and intermediate on-chip interconnects

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hamidreza Hashempour ; Independent Researcher, Tehran, IRAN ; Fabrizio Lombardi

This paper analyzes several delay estimates for metallic carbon nanotubes (CNT) as interconnects of very large scale integrated (VLSI) chips. A study of the 2005 edition of the international technology roadmap (ITRS) [1] for global/intermediate interconnects is presented to highlight the significant issues encountered with the projected performance of copper/aluminum interconnects till 2020. Then a worst case performance analysis of metallic CNTs is presented and compared versus copper interconnects. It is evaluated that the RC delay of CNTs does not meet the future RC delay requirements of on-chip intermediate and global wires.

Published in:

2007 7th IEEE Conference on Nanotechnology (IEEE NANO)

Date of Conference:

2-5 Aug. 2007