To make digital circuits with unreliable devices more reliable has been a big challenge, especially for today's nanoelectronic circuit design. This paper presents a gate replication architecture towards increasing the reliability of individual nano-scale digital logic gates. We focus on deriving the fundamental relationship between gate replication and reliability improvement, and report both theoretical analysis and experimental results.
Published in:
Nanotechnology, 2007. IEEE-NANO 2007. 7th IEEE Conference on
Date of Conference: 2-5 Aug. 2007