By Topic

Towards reliability improvement for nanoelectronic circuits using gate replication

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Chunhong Chen ; Department of Electrical and Computer Engineering, University of Windsor, Ontario, Canada N9B 3P4 ; Feng Zhou

To make digital circuits with unreliable devices more reliable has been a big challenge, especially for today's nanoelectronic circuit design. This paper presents a gate replication architecture towards increasing the reliability of individual nano-scale digital logic gates. We focus on deriving the fundamental relationship between gate replication and reliability improvement, and report both theoretical analysis and experimental results.

Published in:

2007 7th IEEE Conference on Nanotechnology (IEEE NANO)

Date of Conference:

2-5 Aug. 2007