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On the behaviors of multi-island structure for single-electron threshold logic circuits

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2 Author(s)
Paresh Bharkhada ; Department of Electrical and Computer Engineering, University of Windsor, Ontario, Canada N9B 3P4 ; Chunhong Chen

This paper investigates the behaviors of multi-island structure as an alternative redundancy scheme for single-electron tunneling (SET) based digital circuits. In particular, we focus on an SET logic gate (2-input NAND gate) to explore the role of this structure in improving the immunity against random background charges. Also discussed are the parameter selection with multi-island structure, and the difference between this structure and the existing redundancy strategy. Experiments using SIMON simulator show the advantages of the proposed structure.

Published in:

2007 7th IEEE Conference on Nanotechnology (IEEE NANO)

Date of Conference:

2-5 Aug. 2007