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A micro-power low-noise auto-zeroing CMOS amplifier for cortical neural prostheses

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5 Author(s)
Chiu-Hsien Chan ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA ; Wills, J. ; LaCoss, J. ; Granacki, J.J.
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A novel architecture to realize a low-power, low-noise amplifier for cortical neural prostheses is presented. The design consists of a low-noise variable gain amplifier as the first stage, a low-Gm high-pass filter as the second stage, and a low-pass Gm-C amplifier as the last stage. Discrete-time autozeroing is utilized to reduce the offset and noise. The bandwidth and autozeroing frequency of the amplifier is optimized to reduce noise folding. A current division technique is utilized to achieve a low-Gm OTA (Operational Transconductance Amplifier) so that low frequency operation is realized without any external capacitors. All the input pair transistors are biased in sub-threshold operation to reduce power consumption. A cross-couple parallel pair of source degeneration transistors is employed to increase the linearity crucial to neural spike detection. This design achieves variable gain from 470 (55 dB) to 1. In a CMOS 0.18 um process with 1.8 V power supply, the total circuit occupies 0.245 mm2 with 26 uW power consumption and 1.8 kHz bandwidth. Total harmonic distortion is less than 1%, while input noise is 4.24 uVrms within the band of interest.

Published in:

Biomedical Circuits and Systems Conference, 2006. BioCAS 2006. IEEE

Date of Conference:

Nov. 29 2006-Dec. 1 2006

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