By Topic

A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Pulici, P. ; Dipt. di Elettron. e Inf., Politec. di Milano, Milan ; Girardi, A. ; Vanalli, G.P. ; Izzi, R.
more authors

Input-output buffer information specification BIS (IBIS) models are descriptions of the output buffers, used by the printed circuit board (PCB) designer to evaluate the integrity and the quality of the signals. The extension of the use of IBIS models to the system in package (SiP) world is considered. It is found that IBIS models demonstrate some limits for this application, mainly due to the poor stabilization of the supply voltage rails. An example highlighting the IBIS model limits is given. A simple hand analysis of the phenomenon is performed, from which we derive a simple solution to the problem, consisting in an improvement of the structure of the IBIS model. Simulations run making use of the improved models show a much better accuracy of the signal shapes, within 5% of the simulations run with a state-of-the-art transistor level description of the buffers.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:55 ,  Issue: 7 )