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A novel impedance measurement method based on random sampling of voltage and current signals is proposed. This technique dramatically reduces the sampling frequency requirements, thus circumventing the limitations imposed by maximum speed of the analog to digital converter and the signal processing unit. The lowering of the sampling frequencies allows the design and the implementation of an almost all digital architecture by using a simple microprocessor based embedded system and a digital frequency synthesizer. The basic principles are presented, and the implemented algorithms are described. Experimental results show the instrument performances compared to others commercial alternatives.