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With complexities of systems-on-chips (SoCs) rising almost daily, the system designers have been searching for new design methodology that can handle given complexities with decreased times-to-market. The obvious solution that comes to mind is increasing the level of abstraction. However the system designers also care about the system architectures, HW/SW performance, and communication protocols. Furthermore, the transaction-level model (TLM) can satisfy the requests on complex design with relative high simulation speed and well performance evaluation. In this paper, we implement a TLM-based network-on-chip (NoC) platform and share-bus system architecture with SystemC. We also implement the H.263 encoder as the system application, and apply a design methodology at electronic-system level (ESL) to make design modeling, design space exploration and performance evaluation. Out platform is able to evaluate performance in relatively short time, obtain important information and complete the design more instinctively. In addition, we compare and contrast the NoC and share-bus system architectures in terms of evaluation performance. In experimental result, the performance bottleneck in communication congestion is solved well by using the NoC instead of using the share-bus design.