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Memory Models for an Application-Specific Instruction-set Processor Design Flow

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4 Author(s)
Jiying Wu ; Dept. of Inf. Eng. & Comput. Sci., Feng Chia Univ., Taichung ; Chijie Lin ; Desheng Chen ; Yiwen Wang

To optimize system performance for a specific target application, embedded system designers may add some new instructions, called application-specific instructions (ASIs), by automatic design flow. In past days, most application-specific instruction-set processor (ASIP) researches focus on reducing instruction latency to improve performance regardless of the impact of memory access. In this paper, a design flow is proposed to automatically generate ASIs and to compare the performance between considering register transferring and regardless of it. The experiment results show the proposed approach can achieve up to 14% performance improvement and 10% memory access reduction comparing to no register transferring consideration.

Published in:

Embedded Software and Systems, 2008. ICESS '08. International Conference on

Date of Conference:

29-31 July 2008