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An application-specific instruction-set processor (ASIP) is a technique that exploits special characteristics of application(s) to meet the desired performance, cost and power requirements. The generation and selection of Application-Specific Instructions (ASIs) dramatically affect the quality of an ASIP with design constraints such as number of register file I/Os and hardware cost. In this paper, a design flow is developed to automatically combine the disjoint operations as an ASI to enrich the selection varieties. The operation cover-ratio and the ASI latency model are used to select profitable ASIs so that the performance can be improved. The experimental results show the maximal 1.64x speed up can be obtained under hardware cost less than 8000 LEs in Altera FPGA.