By Topic

The description of Serial ATA bus_ Protocol and the design of Serial ATA bus control chip HPT183

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Wei Chang ; Software Coll., Northeastern Univ., Shenyang ; Zhenhua Tan ; Xiaoxing Gao ; Guiran Chang

In a PC system, external storage interface is still a bottleneck in spite of its continuous improving performance, in contrast to the fast development of CPU, memory, graphic chips. The transfer rate in ATA protocol has been improved drastically from the beginning 3.3MB/s to current 133MB/s, but the plate electrode of a parallel interface is inevitably puzzled by clock skew, which limit the increasing of frequency and transfer rate can not be improved. Serial ATA protocol is compatible with Parallel ATA protocol in software layer. Its transfer rate is improved greatly due to serial interface with embedded clock. This paper will discuss the differences between Parallel ATA protocol and serial ATA protocol, and describe the hierarchical classification of serial ATA protocol model. Last a design for HPT183, a parallel/serial ATA bridge connection chip, will be put forward and the test performance index for this chip is also provided.

Published in:

Intelligent Control and Automation, 2008. WCICA 2008. 7th World Congress on

Date of Conference:

25-27 June 2008