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Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application

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4 Author(s)
Seung Wook Yoon ; Inst. of Microelectron., Singapore ; Ganesh, V.P. ; Yak Long Lim, S. ; Kripesh, V.

This paper is for process development of assembly technologies used to fabricate the 3-D silicon carrier system-in-package (SiP). The five assembly technologies are wafer thinning, thin flip chip attach on silicon carrier, ultra low loop wire bonding, glass cap fabrication and sealing, and silicon carrier stacking. The developed SiP has three silicon carriers with four flip chip and one wire bond die chip attached to them and the carrier is stacked one above the other to form the 3-D silicon carrier SiP. Eight-inch bumped wafer thinning down to less than 100 mum, lower flip chip interconnect height between the chip and the carrier down to 35 mum, 40-50- mum low loop wire bonding on overhang by direct reverse wire bonding method using 1- mil-di- ameter Au wire are achieved. And investigation of three types of thin film metallization systems for wirebonding and investigation of two different methods in fabricating glass cap are also studied.

Published in:

Advanced Packaging, IEEE Transactions on  (Volume:31 ,  Issue: 3 )