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Pre-silicon yield estimators for ASIC products have the potential for improved accuracy based on retrospective critical area and yield analysis of completed designs. A prototype closed-loop system, in which a database of observed yield and computed critical areas is continuously compiled and updated, is described in this paper. The database allows a yield model based on circuit content, which is available at the time of quote, but before the physical layout, to be optimized to more accurately reflect a technology's random defect sensitivities. Confining one's observations to the mature 130-nm technology minimizes the inclusion of systematic defects in the observed yield and allows for a more complete view of the random defect component of yield loss.