By Topic

A Low-Power, High-Suppression V-band Frequency Doubler in 0.13 \mu m CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Dong Yun Jung ; Intell. Radio Eng. Center (IREC), Inf. & Commun. Univ. (ICU), Daejeon ; Chul Soon Park

A V-band frequency doubler monolithic microwave integrated circuit with a current re-use buffer amplifier is presented. The circuit is designed and fabricated using 0.13 mum CMOS technology. The buffer amplifier uses a current re-use topology, which adopts series connection of two common source amplifiers for low dc power consumption. The suppression of the fundamental frequency is obtained by shunting the input frequency at the output node of the doubler and the drain nodes of two common-source stages of the buffer amplifier. The fabricated frequency doubler exhibits an output power of -4.45 dBm and a conversion gain of -0.45 dB at input frequency of 27.1 GHz with an input power of -4 dBm. The suppression of the fundamental signal is 49.2 dB. The total dc power dissipation is 9 mW while the buffer amplifier consumes 5 mW. The integrated circuit size including pads is 1.24 mm times 0.75 mm. To our knowledge, this is the highest suppression with low-power dissipation among V-band frequency doublers.

Published in:

Microwave and Wireless Components Letters, IEEE  (Volume:18 ,  Issue: 8 )