By Topic

Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Wang, Grace Huiqi ; Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore (NUS), Singapore ; Toh, Eng-Huat ; Xincai Wang ; Seng, D.H.L.
more authors

We report, for the first time, a simple and cost effective co-integration of strained p and n-FETs using tin (Sn) and mono-carbon (C) implant in Source/Drain (S/D) of p- and n-FETs, respectively, to induce beneficial strain. For the first time, a single laser anneal step was employed to substitutionally incorporate the Sn and C atoms simultaneously into lattice sites. 7 at.% substitutional Sn concentration (the equivalent of adding 35% Ge to SiGe S/D stressors) was achieved in the Si0.7Ge0.3S/D of Si channel p-FET. A significant enhancement of up to 150% in hole mobility and 71% in drive current for a 50 nm gate length device was observed. Mono C implanted S/D n-FETs show 19% current drive increase. With the simultaneous integration of Ni based FUSI gate, we provide a highly useful extension to future S/D technology for further ID,sat and mobility improvement.

Published in:

VLSI Technology, 2008 Symposium on

Date of Conference:

17-19 June 2008